Memory devices such as MRAM have been continuously scaled down in size to accommodate complex device requirements and low power consumption demands. However, the smaller form factor has also increased the complexity of memory device fabrication. Critical dimensions (CD) of memory cells are smaller compared to normal back-end-of-line (BEOL) process variations. Embedded magnetoresistive non-volatile memory (eMRAM) is a film stack designed for both code storage and working memory to enable efficient memory sub-systems that can be power cycled without any energy or performance penalty.
To achieve a desired cell size, the semiconductor industry is pushing to embed a magnetic tunnel junction (MTJ), between metal layers with tight pitch, where there is typically a vertical dimension constraint, for example, a via height of 100 nm for a 90 nm pitch and 75 nm for a 80 nm pitch interconnect. MTJ is composed of at least two ferromagnetic layers separated by an insulating tunnel barrier. A MTJ minimum height including a bottom electrode (BE) is 120 nm. It is not possible to insert MTJ between a metal level Mx and Mx+1.
For tight pitch interconnects less than 100 nm, a titanium nitride (TiN) metal hard mask is used for trench and via patterning. TiN removal is performed with a wet cleaning after trench etching and increases the risk of unwanted interaction with the MTJ.
A need therefore exists for simplified methodology for inserting a MTJ between Mx and Mx+2 levels, and the resulting device.